1. Field of the Invention
The present invention relates generally to techniques for designing and optimizing semiconductor devices and, in particular, to automated techniques for substituting low Vt transistor, gate or cell instances in a semiconductor design.
2. Description of the Related Art
A major challenge faced in the design of semiconductor devices, such as in the design of high-speed microprocessors, is to identify methods of increasing clock speeds for the processor while also managing semiconductor device process limitations. For example, use of low threshold voltage transistors (low Vt) may allow increases in operating frequency but may also negatively impact other design factors, such as leakage current, noise, and minimum timing design requirements. Accordingly, wholesale use of low Vt transistors is undesirable, and often impossible. Ad hoc substitution of low Vt transistors in semiconductor design is impractical, particularly in large-scale designs that include tens of millions of transistors. Accordingly, there is a need for improved techniques whereby low Vt transistors may be selectively substituted in a semiconductor design, while appropriately managing other design factors.
It has been discovered that the performance of an integrated circuit design, whether embodied as a design encoding or as a fabricated integrated circuit, can be improved by selectively substituting low Vt transistors in a way that prioritizes substitution opportunities based on multi-path timing analysis and evaluates such opportunities based on one or more substitution constraints. By valuing, in a prioritization of substitution opportunities, contributions for all or substantially all timing paths through the substitution opportunity that violate a max-time constraint, repeated passes through a timing analysis phase can be advantageously avoided or limited. In addition, by recognizing one or more constraints on actual low Vt substitutions, particular noise-oriented constraints, the scope of post substitution design analysis can be greatly reduced. In some realizations, substitutions are performed so long as a leakage current budget is not expended. As a result, integrated circuit designs prepared in accordance with the described techniques may exhibit substantial cycle time improvements through judicious selection of gate instances for substitution. In some realizations, improved yields of high grade parts may result.
The developed substitution techniques are, in general, applicable at a variety of levels of device/feature aggregation, such as at the individual device, transistor or FET gate level, at the logic gate or standard cell level, or at larger circuit block levels. In each case, a low Vt instance may be selectively substituted for a standard or nominal Vt instance. Persons of ordinary skill in the art will appreciate that a low Vt logic gate instance or circuit block may, in general, include one or more low Vt devices or transistors. Prioritization and selective substitution may be made at any level of aggregation appropriate to a particular integrated circuit design and/or design environment. For purposes of clarity, much of the description that follows is couched in the context of instances of standard cells that implement logic gates. Accordingly, in some realizations, particular gate instances and low Vt gate instances may correspond to instances of standard cells and timing analyses and substitutions will be performed at levels of aggregation corresponding to such instances and networks thereof. However, more generally, the terminology xe2x80x9cgate instancexe2x80x9d and xe2x80x9clow Vt gate instancexe2x80x9d will be understood to include instances of integrated circuit structures and features ranging from individual instances of devices, transistors or gates, to individual instances of logic gates or flops, to instances of circuit blocks. Of course, not all transistors or other devices of a low Vt logic gate or circuit block need be low Vt transistors or devices and suitable designs, including standard cell designs, for low Vt logic gates or circuit blocks will be understood by persons of ordinary skill in the art.
In view of the foregoing, and without limitation, aspects of an exemplary exploitation of the developed techniques are now described in the context of networks of standard cell logic gate instances, timing analysis thereof, substitution constraints, such as node capacitance limits or RC delay limits at gate inputs, and substitutions with low Vt variants of the standard cells. Based on the description herein, persons of ordinary skill in the art will appreciate suitable exploitations for gate instances at larger or smaller levels of aggregation.